An active matrix substrate for use in a liquid crystal display device, or the like, includes a switching element, such as a thin film transistor (hereinafter, “TFT”), in each pixel. Examples of such a switching element which have been conventionally used in various applications include a TFT which includes an amorphous silicon film as an active layer (hereinafter, “amorphous silicon TFT”) and a TFT which includes a polycrystalline silicon film as an active layer (hereinafter, “polycrystalline silicon TFT”).
Since the mobility of electrons and holes in the polycrystalline silicon film is higher than in the amorphous silicon film, the polycrystalline silicon TFT has a higher ON current, and is capable of operating at a higher speed, than the amorphous silicon TFT. Thus, when an active matrix substrate is fabricated using the polycrystalline silicon TFT, the polycrystalline silicon TFT can also be used for a peripheral circuit, such as a driver and the like, as well as the switching elements. Therefore, there is an advantage that part or entirety of the peripheral circuit, such as a driver and the like, and a display portion can be integrally formed on the same substrate. Also, there is another advantage that the pixel capacitor of a liquid crystal display device, or the like, can be charged within a shorter switching time.
However, fabrication of the polycrystalline silicon TFT requires complicated steps, including a laser crystallization step for crystallization of the amorphous silicon film as well as a heat anneal step, an ion doping step, etc. These steps disadvantageously increase the fabrication cost per unit area of the substrate. Therefore, the polycrystalline silicon TFT has been mainly used in middle-size and small-size liquid crystal display devices.
On the other hand, the amorphous silicon film can be formed more easily than the polycrystalline silicon film and is therefore suitable to larger display sizes. Thus, the amorphous silicon TFT is suitably used in an active matrix substrate of a device of which a large area is demanded. In many active matrix substrates for liquid crystal television displays, the amorphous silicon TFT is used, notwithstanding it has a lower ON current than the polycrystalline silicon TFT.
However, when the amorphous silicon TFT is used, improvement in performance is limited because the mobility is low in the amorphous silicon film. Particularly, in recent years, improvement in display quality and reduction in power consumption as well as increase in display size have been highly demanded of liquid crystal display devices, such as liquid crystal television displays. The amorphous silicon TFT has a difficulty in sufficiently meeting such a demand.
To realize a TFT of higher performance with a reduced number of fabrication steps and a reduced fabrication cost, uses of other materials than amorphous silicon and polycrystalline silicon for the material of the active layer have been attempted. Patent Document 1, Patent Document 2, and Non-patent Document 1 propose that a microcrystalline silicon (μc-Si) film is used to form an active layer of a TFT. Such a TFT is called “microcrystalline silicon TFT”.
The microcrystalline silicon film is a silicon film which contains microcrystalline grains in its inside. The grain boundary of the microcrystalline grains is mainly composed of an amorphous phase. Specifically, the grain boundary is in a state where the crystalline phase formed of microcrystalline grains and the amorphous phase are mixed. The size of each microcrystalline grain is smaller than the size of the crystal grains contained in the polycrystalline silicon film. Also, as will be described in detail later, in the microcrystalline silicon film, each microcrystalline grain has the shape of, for example, a column grown from the substrate surface.
The microcrystalline silicon film can be formed only by a film formation step with the use of a plasma CVD method. As the material gas, a silane gas diluted with a hydrogen gas can be used. In the case of forming a polycrystalline silicon film, after formation of an amorphous silicon film with the use of a CVD apparatus or the like, the step of crystallizing the amorphous silicon film by laser or heat (annealing step) is necessary. On the other hand, in the case of forming a microcrystalline silicon film, a microcrystalline silicon film which includes a basic crystalline phase can be formed by a CVD apparatus or the like, and thus, the annealing step with laser or heat can be omitted. Since the microcrystalline silicon film thus can be formed by a smaller number of steps than that required for the formation of the polycrystalline silicon film, the microcrystalline silicon TFT can be fabricated with substantially the same degree of productivity as that of the amorphous silicon TFT, i.e., with substantially the same number of steps and substantially the same fabrication cost. Also, a microcrystalline silicon TFT can be fabricated using an apparatus designed for fabrication of the amorphous silicon TFT.
Since the microcrystalline silicon film has a higher mobility than the amorphous silicon film, using the microcrystalline silicon film can realize a higher ON current than the amorphous silicon TFT. Since the microcrystalline silicon film can be formed without complicated steps as required in the formation of the polycrystalline silicon film, larger areas can easily be realized.
Patent Document 1 describes using a microcrystalline silicon film as the active layer of a TFT, whereby the ON current achieved is 1.5 times that achieved in an amorphous silicon TFT. Non-patent Document 1 describes using a semiconductor film composed of microcrystalline silicon and amorphous silicon, whereby a TFT is obtained in which the ON/OFF current ratio is 106, the mobility is about 1 cm2/Vs, and the threshold is about 5 V. This value of the mobility is greater than that of the amorphous silicon TFT. Note that the TFT described in Non-patent Document 1 includes an amorphous silicon layer which is provided on a microcrystalline silicon layer in order to reduce the OFF current. Patent Document 2 discloses an inverted staggered (bottom gate structure) TFT in which microcrystalline silicon is used.
TFTs in which a metal oxide semiconductor is used as a new material that can replace silicon, such as Zn—O based semiconductor (ZnO) films and In—Ga—Zn—O based semiconductor (IGZO) films, have been proposed. Patent Document 3 describes using a semiconductor layer made of ZnO, which leads to a TFT that is characterized in that the ON/OFF current ratio is 4.5×105, the mobility is about 150 cm2/Vs, and the threshold is about 1.3 V. This mobility value is much higher than the mobility of an amorphous silicon TFT. Patent Document 2 describes using a semiconductor layer made of IGZO, which leads to a TFT that is characterized in that the mobility is about 5.6 to 8.0 cm2/Vs and the threshold is about −6.6 to −9.9 V. Also, this mobility is much higher than the mobility of an amorphous silicon TFT.
On the other hand, an active matrix substrate usually includes a short ring between wires, such as source and gate bus lines, in order to prevent electrostatic damage to elements, wires, etc. In conventional devices, as a short ring, a conductive line is formed around the gate bus lines and the source bus lines such that these lines are all electrically coupled together. However, such a short ring need to be removed before a driver for driving, and the like, is mounted on the substrate, and therefore, an element cannot be sufficiently protected from static electricity which would occur in a mounting step.
As a solution to this problem, forming a short ring with the use of a semiconductor film which is the same as the semiconductor layer of the TFT has been proposed. For example, Patent Documents 4 to 6 disclose forming two-terminal elements (hereinafter, also referred to as “short ring diodes”) with the use of a semiconductor film to form a short ring between source bus lines and/or between gate bus lines. In Patent Document 4, an amorphous silicon film is used as the semiconductor film. In Patent Documents 5 and 6, a polysilicon film (polycrystalline silicon film) is used as the semiconductor film.
FIG. 25(a) is a plan view of an active matrix substrate disclosed in Patent Document 4. The active matrix substrate 1000 includes a plurality of gate bus lines 1014 which are arranged in parallel with one another, a plurality of source bus lines 1010 which are perpendicular to the gate bus lines 1014, pixel electrodes (not shown) which are respectively provided in rectangular regions enclosed by the gate bus lines 1014 and the source bus lines 1010, and thin film transistors 1018 provided in the vicinity of the intersections of the gate bus lines 1014 and the source bus lines 1010. The thin film transistors 1018 function as switching elements for the respective pixels. The gate bus lines 1014 are connected to gate terminals 1016. The source bus lines 1010 are connected to source terminals 1012. Short ring diodes 1020 which are formed with the use of a semiconductor film that is the same as the semiconductor layer of the thin film transistors 1018 are provided between adjacent ones of the gate bus lines 1014 and between adjacent ones of the source bus lines 1010. The diodes 1020 have a configuration in which the source and the gate of the TFT are short-circuited and are also referred to as “TFT-type diodes”.
In the active matrix substrate 1000, when external static electricity comes in any of the terminals 1012, 1016, the gate of the diode 1020 which is connected to that gate 1012, 1016 opens so that the charges sequentially diffuse to the adjacent lines 1010, 1014. As a result, all of the source bus lines 1010 and the gate bus lines 1014 become equipotential so that the thin film transistors 1018 can be prevented from being damaged by static electricity.
FIG. 25(b) is a schematic cross-sectional view of a TFT-type diode 1020 disclosed in Patent Document 4. The diode 1020 includes a gate electrode 1111, a semiconductor layer 1006 provided on the gate electrode 1111 with the intervention of a gate insulating film 1005 therebetween, and a first electrode (source electrode) 1131 and a second electrode (drain electrode) 1132 which are electrically connected to respective ones of the opposite sides of the semiconductor layer 1006. A contact layer 1007 is provided between the semiconductor layer 1006 and the first and second electrodes 1131, 1132. The first electrode 1131 is connected to the gate electrode 1111 in a contact hole 1133. Part of the semiconductor layer 1006 lying between the two electrodes 1131, 1132, i.e., portion 1006c, extends above the gate electrode 1111.
In the diode 1020 having such a structure, when a positive potential, relative to the potential of the second electrode 1132 which serves as a reference (0 V), is supplied to the first electrode 1131, the gate electrode 1111 also has a positive potential. Accordingly, part of the semiconductor layer 1006 extending above the gate electrode 1111, i.e., portion 1006c, has a decreased electric resistance, so that a channel is formed. As a result, an electric current flows between the first electrode 1131 and the second electrode 1132.